Design and Integration of HBM/LPDDR Subsystems in Chiplet SoCs

  • Authors

    • VenkataKrishna Brahmam Pogadadanda Senior RTL Design Engineer at AMD-Xilinx, USA. Author

    DOI:

    https://doi.org/10.67228/30715717/IJDEIC-2024PII3K9M

    Published 09-12-2024

  • Chiplet SoC, HBM, LPDDR, Memory Subsystem, Advanced Packaging, Interposer, Die-to-Die Communication, Power Optimization, AI Accelerators, Heterogeneous Integration

    Issue

    Vol. 7 No. 2 (2024)

    Section

    Articles

  • Abstract

    Chiplet-based SoC architectures are basically game changers to deliver the increasing needs of performance, scalability, and energy-efficiency of modern-day computing devices. Breaking down the highly complex SoCs into small functional chiplets not only helps in increasing yield and reducing the overall manufacturing cost but also allows the integration of different types of processors, accelerators, and memory subsystems in the form of chiplets. This way, High-Bandwidth Memory (HBM) and Low-Power Double Data Rate (LPDDR) memories continue to be very instrumental in delivering the bandwidth, latency, and power efficiency that are essential for AI, HPC, mobile platforms, and edge device applications. Nevertheless, bringing HBM and LPDDR subsystems in chiplet architectures not only increases interconnect and thermal management complexities but also poses challenges such as signal integrity, power delivery, memory coherence, and packaging constraints. The proposed methodology in this paper for HBM/LPDDR subsystem integration in chiplet SoCs is based on the use of highly optimized die-to-die interfaces, advanced packaging technologies, hierarchical memory management, and adaptive power-control strategies. A case study is carried out that shows a better bandwidth utilization, smaller access latencies, and higher energy-efficiency than the traditional monolithic designs. These results emphasize scalable memory-centric chiplet architectures that can serve as the base for future heterogeneous.

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