Power-Aware RTL Design Techniques for High-Performance ASICs

Abstract

The increase in transistor density, frequency, and integration level inside circuits have exposed power consumption issues in high-end ASIC design. Hence, power has become one of the key design objectives together with performance and area of silicon. Power optimization at the RTL level has brought out as the most efficient measure since almost 60% of the chip's power can be saved through early power optimization done at Register Transfer Level (RTL) design phase and at the same time it is cost effective as the redesign time at later stages is totally avoided. In this paper, a variety of power-aware RTL techniques and methodologies have been studied and their implementation in ASIC through which power dissipation both dynamic as well as leakage can be curtailed using clock gating, power gating, operand isolation, multi-threshold voltage design, dynamic voltage and frequency scaling (DVFS), resource sharing, and optimized state machine encoding collectively, have been identified. Besides these, the paper also discusses the compromise between power, performance, and area (PPA) and how proper RTL libraries can aid in energy efficiency without considerably tapping computational throughput. Besides case study assessment, simulation-based power analysis and synthesis-driven optimization have been combined to highlight the practical viability of these power-saving methodologies of the high-performance ASICs. The conclusion drawn from the results of the study was that power consumption in the early right RTL stage can be low significantly even after maintaining timing and functional accuracy. Also, the paper talks about future trends, e.g., AI-based power optimization, adaptive low-power architectures, and new semiconductor technologies which are likely to influence the new generation of energy efficient ASIC design.